A fault tolerance technique for combinational circuits based on selective-transistor redundancy AT Sheikh, AH El-Maleh, MES Elrabaa, SM Sait IEEE Transactions on Very Large Scale Integration (VLSI) Systems 25 (1), 224-237, 2016 | 128 | 2016 |
Binary particle swarm optimization (BPSO) based state assignment for area minimization of sequential circuits AH El-Maleh, AT Sheikh, SM Sait Applied soft computing 13 (12), 4832-4840, 2013 | 86 | 2013 |
Efficient variants of square contour algorithm for blind equalization of QAM signals AT Sheikh, SA Sheikh International Journal of Electronics and Communication Engineering 3 (3 …, 2009 | 13 | 2009 |
Cell assignment in hybrid CMOS/nanodevices architecture using a PSO/SA hybrid algorithm SM Sait, AT Sheikh, AH El-Maleh Journal of applied research and technology 11 (5), 653-664, 2013 | 10 | 2013 |
Method of fault tolerance in combinational circuits AH El-Maleh, AT Sheikh US Patent 10,013,296, 2018 | 6 | 2018 |
An integrated fault tolerance technique for combinational circuits based on implications and transistor sizing AT Sheikh, AH El-Maleh Integration 58, 35-46, 2017 | 6 | 2017 |
Resilient and Secure System on Chip with Rejuvenation in the Wake of Persistent Attacks AT Sheikh, A Shoker, P Esteves-Verissimo Proceedings of the 16th European Workshop on System Security, 37-43, 2023 | 5 | 2023 |
Double modular redundancy (dmr) based fault tolerance technique for combinational circuits AT Sheikh, AH El-Maleh Journal of Circuits, Systems and Computers 27 (06), 1850097, 2018 | 4 | 2018 |
ResiLogic: Leveraging Composability and Diversity to Design Fault and Intrusion Resilient Chips AT Sheikh, A Shoker, SA Fahmy, P Esteves-Verissimo arXiv preprint arXiv:2409.02553, 2024 | | 2024 |
Resilient and Secure Programmable System-on-Chip Accelerator Offload I Pinto Gouveia, AT Sheikh, A Shoker, SA Fahmy, P Esteves-Verissimo arXiv e-prints, arXiv: 2406.18117, 2024 | | 2024 |
An Integrated Approach for Soft Error Tolerance of Combinational Circuits AT Sheikh PQDT-Global, 2016 | | 2016 |