| BLADE: An in-cache computing architecture for edge devices WA Simon, YM Qureshi, M Rios, A Levisse, M Zapater, D Atienza IEEE Transactions on Computers 69 (9), 1349-1363, 2020 | 65 | 2020 |
| Gem5-x: A gem5-based system level simulation framework to optimize many-core platforms YM Qureshi, WA Simon, M Zapater, D Atienza, K Olcoz 2019 Spring Simulation Conference (SpringSim), 1-12, 2019 | 37 | 2019 |
| BLADE: A bitline accelerator for devices on the edge WA Simon, YM Qureshi, A Levisse, M Zapater, D Atienza Proceedings of the 2019 on Great Lakes Symposium on VLSI, 207-212, 2019 | 28 | 2019 |
| Gem5-X: A Many-Core Heterogeneous Simulation Platform for Architectural Exploration and Optimization YM Qureshi, WA Simon, M Zapater Sancho, K Olcoz, D Atienza Alonso ACM Transactions on Architecture and Code Optimization (TACO) 18 (4), 1-27, 2021 | 19 | 2021 |
| Energy proportionality in near-threshold computing servers and cloud data centers: Consolidating or not? A Pahlevan, YM Qureshi, M Zapater, A Bartolini, D Rossi, L Benini, ... 2018 Design, Automation & Test in Europe Conference & Exhibition (DATE), 147-152, 2018 | 15 | 2018 |
| Alpine: Analog in-memory acceleration with tight processor integration for deep learning J Klein, I Boybat, Y Qureshi, M Dazzi, A Levisse, G Ansaloni, M Zapater, ... IEEE Transactions on Computers, 2022 | 14 | 2022 |
| A product engine for energy-efficient execution of binary neural networks using resistive memories J Vieira, E Giacomin, Y Qureshi, M Zapater, X Tang, S Kvatinsky, ... 2019 IFIP/IEEE 27th International Conference on Very Large Scale Integration …, 2019 | 11 | 2019 |
| Genome sequence alignment-design space exploration for optimal performance and energy architectures YM Qureshi, JM Herruzo, M Zapater, K Olcoz, S Gonzalez-Navarro, ... IEEE Transactions on Computers 70 (12), 2218-2233, 2020 | 5 | 2020 |
| Design and layout of two stage high bandwidth operational amplifier YM Qureshi World Academy of Science, Engineering and Technology 71, 2012 | 4 | 2012 |
| Accelerating inference on binary neural networks with digital RRAM processing J Vieira, E Giacomin, Y Qureshi, M Zapater, X Tang, S Kvatinsky, ... VLSI-SoC: New Technology Enabler: 27th IFIP WG 10.5/IEEE International …, 2020 | 2 | 2020 |
| Full System Exploration of On-Chip Wireless Communication on Many-Core Architectures R Medina, J Kein, Y Qureshi, M Zapater, G Ansaloni, D Atienza 2022 IEEE 13th Latin America Symposium on Circuits and System (LASCAS), 1-4, 2022 | | 2022 |
| Architecture Exploration and Optimization of Heterogeneous Many-Core Compute and Memory Architectures with Architectural Extensions YM Qureshi EPFL, 2021 | | 2021 |
| gem-5 eXtensions for RISC-V: Full System Manual J KLEIN, Y QURESHI, M ZAPATER, D ATIENZA | | 2020 |
| ESL MMS Aly, A Aminifar, A Amirshahi, A Andreev, G Ansaloni, A Arza Valdes, ... | | |
Marina ZapaterAssociate Professor at HEIG-VD / HES-SOVerified email at heig-vd.ch
