| A security framework for noc using authenticated encryption and session keys HK Kapoor, GB Rao, S Arshi, G Trivedi Circuits, Systems, and Signal Processing 32, 2605-2622, 2013 | 61 | 2013 |
| An authenticated encryption based security framework for NoC architectures K Sajeesh, HK Kapoor 2011 International Symposium on Electronic System Design, 134-139, 2011 | 40 | 2011 |
| Cost effective routing techniques in 2D mesh NoC using on-chip transmission lines D Deb, J Jose, S Das, HK Kapoor Journal of Parallel and Distributed Computing 123, 118-129, 2019 | 29 | 2019 |
| Energy aware frame based fair scheduling S Moulik, A Sarkar, HK Kapoor Sustainable Computing: Informatics and Systems 18, 66-77, 2018 | 22 | 2018 |
| Analysing the role of last level caches in controlling chip temperature S Chakraborty, HK Kapoor IEEE Transactions on Sustainable Computing 3 (4), 289-305, 2018 | 20 | 2018 |
| Improving the lifetime of non-volatile cache by write restriction S Agarwal, HK Kapoor IEEE Transactions on Computers 68 (9), 1297-1312, 2019 | 18 | 2019 |
| Towards near data processing of convolutional neural networks P Das, S Lakhotia, P Shetty, HK Kapoor 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 17 | 2018 |
| Victim retention for reducing cache misses in tiled chip multiprocessors S Das, HK Kapoor Microprocessors and Microsystems 38 (4), 263-275, 2014 | 17 | 2014 |
| TARTS: A temperature-aware real-time deadline-partitioned fair scheduler S Moulik, A Sarkar, HK Kapoor Journal of Systems Architecture 112, 101847, 2021 | 16 | 2021 |
| Dpfair scheduling with slowdown and suspension S Moulik, A Sarkar, HK Kapoor 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 16 | 2018 |
| Modelling and verification of delay-insensitive circuits using CCS and the Concurrency Workbench HK Kapoor, MB Josephs Information Processing Letters 89 (6), 293-296, 2004 | 16 | 2004 |
| Reuse-distance-aware write-intensity prediction of dataless entries for energy-efficient hybrid caches S Agarwal, HK Kapoor IEEE Transactions on Very Large Scale Integration (VLSI) Systems 26 (10 …, 2018 | 15 | 2018 |
| Restricting writes for energy-efficient hybrid cache in multi-core architectures S Agarwal, HK Kapoor 2016 IFIP/IEEE International Conference on Very Large Scale Integration …, 2016 | 15 | 2016 |
| Exploration of migration and replacement policies for dynamic NUCA over tiled CMPs S Das, HK Kapoor 2015 28th International Conference on VLSI Design, 141-146, 2015 | 15 | 2015 |
| Fault tolerance in network on chip using bypass path establishing packets S Priya, S Agarwal, HK Kapoor 2018 31st International Conference on VLSI Design and 2018 17th …, 2018 | 14 | 2018 |
| Targeting inter set write variation to improve the lifetime of non-volatile cache using fellow sets S Agarwal, HK Kapoor 2017 IFIP/IEEE International Conference on Very Large Scale Integration …, 2017 | 14 | 2017 |
| Exploring the role of large centralised caches in thermal efficient chip design S Chakraborty, HK Kapoor ACM Transactions on Design Automation of Electronic Systems (TODAES) 24 (5 …, 2019 | 13 | 2019 |
| Static energy reduction by performance linked cache capacity management in tiled cmps HK Kapoor, S Das, S Chakraborty Proceedings of the 30th Annual ACM Symposium on Applied Computing, 1913-1918, 2015 | 12 | 2015 |
| Dynamic Associativity Management using Fellow Sets S Das, HK Kapoor International Symposium on Electronic System Design (ISED), 2013 | 12 | 2013 |
| Formal approach for DVS-based power management for multiple server system in presence of server failure and repair L Chandnani, HK Kapoor IEEE Transactions on Industrial Informatics 9 (1), 502-513, 2012 | 12 | 2012 |
