Gert Jervan
Gert Jervan
School of IT, Tallinn University of Technology (TalTech)
Verified email at - Homepage
Cited by
Cited by
Test cost minimization for hybrid BIST
G Jervan, Z Peng, R Ubar
Proceedings IEEE International Symposium on Defect and Fault Tolerance in …, 2000
Test time minimization for hybrid BIST of core-based systems
Jervan, Eles, Peng, Ubar, Jenihhin
2003 Test Symposium, 318-323, 2003
High-level and hierarchical test sequence generation
G Jervan, Z Peng, O Goloubeva, MS Reorda, M Violante
Seventh IEEE International High-Level Design Validation and Test Workshop …, 2002
Turbo Tester: a CAD system for teaching digital test
G Jervan, A Markus, P Paomets, J Raik, R Ubar
Microelectronics Education: Proceedings of the 2 nd European Workshop held …, 1998
A hybrid BIST architecture and its optimization for SoC testing
G Jervan, Z Peng, R Ubar, H Kruus
Proceedings International Symposium on Quality Electronic Design, 273-279, 2002
Augmented coaching ecosystem for non-obtrusive adaptive personalized elderly care on the basis of cloud-fog-dew computing paradigm
Y Gordienko, S Stirenko, O Alienin, K Skala, Z Sojat, A Rojbi, JRL Benito, ...
2017 40th International Convention on Information and Communication …, 2017
From online fault detection to fault management in Network-on-Chips: A ground-up approach
SP Azad, B Niazmand, K Janson, N George, AS Oyeniran, T Putkaradze, ...
2017 IEEE 20th International Symposium on Design and Diagnostics of …, 2017
Hybrid BIST time minimization for core-based systems with STUMPS architecture
G Jervan, P Eles, Z Peng, R Ubar, M Jenihhin
Proceedings 18th IEEE Symposium on Defect and Fault Tolerance in VLSI …, 2003
Hybrid BIST optimization using reseeding and test set compaction
G Jervan, E Orasson, H Kruus, R Ubar
Microprocessors and Microsystems 32 (5-6), 254-262, 2008
Energy minimization for hybrid BIST in a system-on-chip test environment
R Ubar, T Shchenova, G Jervan, Z Peng
European Test Symposium (ETS'05), 2-7, 2005
Fast test cost calculation for hybrid BIST in digital systems
E Orasson, R Raidma, R Ubar, G Jervan, Z Peng
Proceedings Euromicro Symposium on Digital Systems Design, 318-325, 2001
QoT assessment of the optical spectrum as a service in disaggregated network scenarios
K Kaeval, T Fehenberger, J Zou, SL Jansen, K Grobe, H Griesser, ...
Journal of optical communications and networking 13 (10), E1-E12, 2021
Logic-based implementation of fault-tolerant routing in 3D network-on-chips
B Niazmand, SP Azad, J Flich, J Raik, G Jervan, T Hollstein
2016 Tenth IEEE/ACM International Symposium on Networks-on-Chip (NOCS), 1-8, 2016
Holistic approach for fault-tolerant network-on-chip based many-core systems
SP Azad, B Niazmand, J Raik, G Jervan, T Hollstein
arXiv preprint arXiv:1601.07089, 2016
CAESAR-MPSoC: Dynamic and efficient MPSoC security zones
SP Azad, M Tempelmeier, G Jervan, J Sepúlveda
2019 IEEE Computer Society Annual Symposium on VLSI (ISVLSI), 477-482, 2019
Miniaturized wireless monitor for long-term monitoring of newborns
M Leier, G Jervan
2014 14th Biennial Baltic Electronic Conference (BEC), 193-196, 2014
Teaching modeling in SysML/UML and problems encountered
H Kruus, T Robal, G Jervan
2014 25th EAEEIE Annual Conference (EAEEIE), 33-36, 2014
Power-constrained hybrid BIST test scheduling in an abort-on-first-fail test environment
Z He, G Jervan, Z Peng, P Eles
8th Euromicro Conference on Digital System Design (DSD'05), 83-86, 2005
Test generation: a hierarchical approach
G Jervan, R Ubar, Z Peng, P Eles
System-level Test and Validation of Hardware/Software Systems, 67-81, 2005
A framework for combining concurrent checking and on-line embedded test for low-latency fault detection in NoC routers
P Saltarelli, B Niazmand, J Raik, V Govind, T Hollstein, G Jervan, ...
Proceedings of the 9th International Symposium on Networks-on-Chip, 1-8, 2015
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