| Open Cell Library in 15nm FreePDK Technology M Martins, JM Matos, RP Ribas, A Reis, G Schlinker, L Rech, J Michelsen Proceedings of the 2015 Symposium on International Symposium on Physical …, 2015 | 273 | 2015 |
| Boolean factoring with multi-objective goals MGA Martins, L Rosa Jr, AB Rasmussen, RP Ribas, A Reis Computer Design (ICCD), 2010 IEEE International Conference on, 229-234, 2010 | 58 | 2010 |
| Exploring the use of approximate TMR to mask transient faults in logic with low area overhead IAC Gomes, MGA Martins, AI Reis, FL Kastensmidt Microelectronics Reliability 55 (9-10), 2072-2076, 2015 | 56 | 2015 |
| Power consumption analysis in static cmos gates A Wiltgen, KA Escobar, AI Reis, RP Ribas 2013 26th Symposium on Integrated Circuits and Systems Design (SBCCI), 1-6, 2013 | 53 | 2013 |
| Classifying n-input Boolean functions VP Correia, AI Reis VII Workshop Iberchip, 58, 2001 | 51 | 2001 |
| DAG based library-free technology mapping FS Marques, LS Rosa Jr, RP Ribas, SS Sapatnekar, AI Reis Proceedings of the 17th ACM Great Lakes symposium on VLSI, 293-298, 2007 | 47 | 2007 |
| BTI, HCI and TDDB aging impact in flip–flops C Nunes, PF Butzen, AI Reis, RP Ribas Microelectronics Reliability 53 (9-11), 1355-1359, 2013 | 43 | 2013 |
| KL-cuts: a new approach for logic synthesis targeting multiple output blocks O Martinello, FS Marques, RP Ribas, AI Reis Design, Automation & Test in Europe Conference & Exhibition (DATE), 2010 …, 2010 | 42 | 2010 |
| Graph-based transistor network generation method for supergate design VN Possani, V Callegaro, AI Reis, RP Ribas, F de Souza Marques, ... IEEE Transactions on Very Large Scale Integration (VLSI) Systems 24 (2), 692-705, 2015 | 41 | 2015 |
| Library free technology mapping AI Reis, R Reis, D Auvergne, M Robert VLSI: Integrated Systems on Silicon: IFIP TC10 WG10. 5 International …, 1997 | 41 | 1997 |
| Exact lower bound for the number of switches in series to implement a combinational logic cell FR Schneider, RP Ribas, SS Sapatnekar, AI Reis Computer Design: VLSI in Computers and Processors, 2005. ICCD 2005 …, 2005 | 37 | 2005 |
| Associating CMOS transistors with BDD arcs for technology mapping A Reis, M Robert, D Auvergne, R Reis Electronics Letters 31 (14), 1118-1120, 1995 | 35 | 1995 |
| Advanced technology mapping for standard-cell generators V Correia, A Reis Proceedings of the 17th symposium on Integrated circuits and system design …, 2004 | 34 | 2004 |
| Semi-custom NCL Design with Commercial EDA Frameworks: Is it Possible? M Moreira, N Calazans, A Silva, M Martins, A Reis, R Ribas International Symposium on Asynchronous Circuits and Systems (ASYNC), Potsdam, 2014 | 33 | 2014 |
| Standby power consumption estimation by interacting leakage current mechanisms in nanoscaled CMOS digital circuits PF Butzen, LS da Rosa Jr, EJD Chiappetta Filho, AI Reis, RP Ribas Microelectronics Journal 41 (4), 247-255, 2010 | 32 | 2010 |
| Switch level optimization of digital CMOS gate networks LS da Rosa, FR Schneider, RP Ribas, AI Reis 2009 10th International Symposium on Quality Electronic Design, 324-329, 2009 | 32 | 2009 |
| Using only redundant modules with approximate logic to reduce drastically area overhead in TMR I Gomes, M Martins, A Reis, FL Kastensmidt Test Symposium (LATS), 2015 16th Latin-American, 1-6, 2015 | 27 | 2015 |
| Fast disjoint transistor networks from BDDs LS da Rosa Junior, FS Marques, TMG Cardoso, RP Ribas, ... Proceedings of the 19th annual symposium on Integrated circuits and systems …, 2006 | 27 | 2006 |
| Covering strategies for library free technology mapping AI Reis Proceedings. XII Symposium on Integrated Circuits and Systems Design (Cat …, 1999 | 27 | 1999 |
| Factored forms for memristive material implication stateful logic FS Marranghello, V Callegaro, MGA Martins, AI Reis, RP Ribas IEEE Journal on Emerging and Selected Topics in Circuits and Systems 5 (2 …, 2015 | 26 | 2015 |
Renato P. RibasProfessor, Informatics Institute - Federal Univ. of Rio Grande do SulVerified email at ufrgs.br
