| An energy-efficient nonvolatile in-memory computing architecture for extreme learning machine by domain-wall nanowire devices Y Wang, H Yu, L Ni, GB Huang, M Yan, C Weng, W Yang, J Zhao IEEE Transactions on Nanotechnology 14 (6), 998-1012, 2015 | 94 | 2015 |
| An energy-efficient digital ReRAM-crossbar-based CNN with bitwise parallelism L Ni, Z Liu, H Yu, RV Joshi IEEE Journal on Exploratory solid-state computational devices and circuits 3 …, 2017 | 89 | 2017 |
| An energy-efficient matrix multiplication accelerator by distributed in-memory computing on binary RRAM crossbar L Ni, Y Wang, H Yu, W Yang, C Weng, J Zhao 2016 21st Asia and South Pacific Design Automation Conference (ASP-DAC), 280-285, 2016 | 69 | 2016 |
| DW-AES: A domain-wall nanowire-based AES for high throughput and energy-efficient data encryption in non-volatile memory Y Wang, L Ni, CH Chang, H Yu IEEE Transactions on Information Forensics and Security 11 (11), 2426-2440, 2016 | 60 | 2016 |
| Distributed in-memory computing on binary RRAM crossbar L Ni, H Huang, Z Liu, RV Joshi, H Yu ACM Journal on Emerging Technologies in Computing Systems (JETC) 13 (3), 1-18, 2017 | 57 | 2017 |
| A highly parallel and energy efficient three-dimensional multilayer CMOS-RRAM accelerator for tensorized neural network H Huang, L Ni, K Wang, Y Wang, H Yu IEEE Transactions on Nanotechnology 17 (4), 645-656, 2017 | 40 | 2017 |
| Memory device, and data processing method based on multi-layer RRAM crossbar array H Yu, Y Wang, J Zhao, W Yang, S Xiao, L Ni US Patent 10,459,724, 2019 | 29 | 2019 |
| An energy-efficient and high-throughput bitwise CNN on sneak-path-free digital ReRAM crossbar L Ni, Z Liu, W Song, JJ Yang, H Yu, K Wang, Y Wang 2017 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2017 | 26 | 2017 |
| Optimizing Boolean embedding matrix for compressive sensing in RRAM crossbar Y Wang, X Li, H Yu, L Ni, W Yang, C Weng, J Zhao 2015 IEEE/ACM International Symposium on Low Power Electronics and Design …, 2015 | 15 | 2015 |
| On-line machine learning accelerator on digital RRAM-crossbar L Ni, H Huang, H Yu 2016 IEEE International Symposium on Circuits and Systems (ISCAS), 113-116, 2016 | 12 | 2016 |
| VECBEE: A versatile efficiency–accuracy configurable batch error estimation method for greedy approximate logic synthesis S Su, C Meng, F Yang, X Shen, L Ni, W Wu, Z Wu, J Zhao, W Qian IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2022 | 9 | 2022 |
| Distributed in-memory computing on binary memristor-crossbar for machine learning H Yu, L Ni, H Huang Advances in Memristors, Memristive Devices and Systems, 275-304, 2017 | 9 | 2017 |
| A memristor network with coupled oscillator and crossbar towards L2-norm based machine learning L Ni, H Huang, H Yu 2016 IEEE/ACM International Symposium on Nanoscale Architectures (NANOARCH …, 2016 | 7 | 2016 |
| Non-volatile in-memory computing by spintronics H Yu, L Ni, Y Wang Springer Nature, 2022 | 6 | 2022 |
| An energy-efficient non-volatile in-memory accelerator for sparse-representation based face recognition Y Wang, H Huang, L Ni, H Yu, M Yan, C Weng, W Yang, J Zhao 2015 Design, Automation & Test in Europe Conference & Exhibition (DATE), 932-935, 2015 | 6 | 2015 |
| SEALS: Sensitivity-driven efficient approximate logic synthesis C Meng, X Wang, J Sun, S Tao, W Wu, Z Wu, L Ni, X Shen, J Zhao, ... Proceedings of the 59th ACM/IEEE Design Automation Conference, 439-444, 2022 | 5 | 2022 |
| Revisiting pass-transistor logic styles in a 12nm FinFET technology node J Lappas, A Chinazzo, C Weis, C Xia, Z Wu, L Ni, N Wehn 2022 Design, Automation & Test in Europe Conference & Exhibition (DATE …, 2022 | 4 | 2022 |
| LTNN: An energy-efficient machine learning accelerator on 3D CMOS-RRAM for layer-wise tensorized neural network H Huang, L Ni, H Yu 2017 30th IEEE International System-on-Chip Conference (SOCC), 280-285, 2017 | 4 | 2017 |
| A 3D multi-layer CMOS-RRAM accelerator for neural network H Huang, L Ni, Y Wang, H Yu, Z Wangl, Y Cail, R Huangl 2016 IEEE International 3D Systems Integration Conference (3DIC), 1-5, 2016 | 4 | 2016 |
| A zonotoped macromodeling for eye-diagram verification of high-speed i/o links with jitter and parameter variations L Ni, SM PD, Y Song, C Gu, H Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2015 | 4 | 2015 |
Hao Yu （余浩）SUSTech（南方科技大学）Verified email at sustech.edu.cn
