Benoît Dupont de Dinechin
Benoît Dupont de Dinechin
CTO Kalray
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Cited by
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A clustered manycore processor architecture for embedded and accelerated applications
BD De Dinechin, R Ayrignac, PE Beaucamps, P Couvert, B Ganne, ...
2013 IEEE High Performance Extreme Computing Conference (HPEC), 1-6, 2013
Time-critical computing on a single-chip massively parallel processor
BD De Dinechin, D Van Amstel, M Poulhiès, G Lager
2014 Design, Automation & Test in Europe Conference & Exhibition (DATE), 1-6, 2014
A distributed run-time environment for the kalray mppa®-256 integrated manycore processor
BD de Dinechin, PG de Massas, G Lager, C Léger, B Orgogozo, J Reybert, ...
Procedia Computer Science 18, 1654-1663, 2013
The shift to multicores in real-time and safety-critical systems
S Saidi, R Ernst, S Uhrig, H Theiling, BD de Dinechin
2015 International Conference on Hardware/Software Codesign and System …, 2015
Mixed-criticality scheduling on cluster-based manycores with shared communication and storage resources
G Giannopoulou, N Stoimenov, P Huang, L Thiele, BD de Dinechin
Real-Time Systems 52, 399-449, 2016
Revisiting out-of-SSA translation for correctness, code quality and efficiency
B Boissinot, A Darte, F Rastello, BD de Dinechin, C Guillon
2009 International Symposium on Code Generation and Optimization, 114-125, 2009
Guaranteed services of the NoC of a manycore processor
BD de Dinechin, Y Durand, D van Amstel, A Ghiti
Proceedings of the 2014 International Workshop on Network on Chip …, 2014
Extended cyclostatic dataflow program compilation and execution for an integrated manycore processor
P Aubry, PE Beaucamps, F Blanc, B Bodin, S Carpov, L Cudennec, ...
Procedia Computer Science 18, 1624-1633, 2013
Novel arithmetics in deep neural networks signal processing for autonomous driving: Challenges and opportunities
M Cococcioni, F Rossi, E Ruffaldi, S Saponara, BD de Dinechin
IEEE Signal Processing Magazine 38 (1), 97-110, 2020
Periodic schedules for cyclo-static dataflow
B Bodin, A Munier-Kordon, BD De Dinechin
The 11th IEEE Symposium on Embedded Systems for Real-time Multimedia, 105-114, 2013
K-periodic schedules for evaluating the maximum throughput of a synchronous dataflow graph
B Bodin, A Munier-Kordon, BD de Dinechin
2012 International Conference on Embedded Computer Systems (SAMOS), 152-159, 2012
Kalray MPPA®: Massively parallel processor array: Revisiting DSP acceleration with the Kalray MPPA Manycore processor
BD de Dinechin
2015 IEEE Hot Chips 27 Symposium (HCS), 1-27, 2015
Code generator optimizations for the ST120 DSP-MCU core
BD de Dinechin, F de Ferri, C Guillon, A Stoutchinin
Proceedings of the 2000 International Conference on Compilers, architecture …, 2000
Paving the way towards a highly energy-efficient and highly integrated compute node for the Exascale revolution: the ExaNoDe approach
A Rigo, C Pinto, K Pouget, D Raho, D Dutoit, PY Martinez, C Doran, ...
2017 Euromicro Conference on Digital System Design (DSD), 486-493, 2017
From machine scheduling to VLIW instruction scheduling
BD De Dinechin
ST Journal of Research 1 (2), 1-35, 2004
A mixed-precision fused multiply and add
N Brunie, F De Dinechin, B De Dinechin
2011 Conference Record of the Forty Fifth Asilomar Conference on Signals …, 2011
Network-on-chip service guarantees on the kalray mppa-256 bostan processor
BD de Dinechin, A Graillat
Proceedings of the 2nd international workshop on advanced interconnect …, 2017
Mixed precision fused multiply-add operator
FD De Dinechin, N Brunie, BD De Dinechin
US Patent 9,367,287, 2016
Radiation experiments on a 28 nm single-chip many-core processor and SEU error-rate prediction
V Vargas, P Ramos, V Ray, C Jalier, R Stevens, BD De Dinechin, ...
IEEE Transactions on Nuclear Science 64 (1), 483-490, 2016
Simplex scheduling: More than lifetime-sensitive instruction scheduling
BD de Dinechin
Proc. of the International Conf. on Parallel Architecture and Compiler …, 1994
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