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Arun Kanuparthi
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Hardware and embedded security in the context of internet of things
A Kanuparthi, R Karri, S Addepalli
Proceedings of the 2013 ACM workshop on Security, privacy & dependability …, 2013
1402013
MAGIC: Malicious Aging in Circuits/Cores
N Karimi, A Kanuparthi, X Wang, R Karri, O Sinanoglu
Transactions on Architecture and Code Optimization, 2015
412015
{HardFails}: Insights into {Software-Exploitable} Hardware Bugs
G Dessouky, D Gens, P Haney, G Persyn, A Kanuparthi, H Khattri, ...
28th USENIX Security Symposium (USENIX Security 19), 213-230, 2019
402019
Securing processors against insider attacks: A circuit-microarchitecture co-design approach
J Rajendran, AK Kanuparthi, M Zahran, SK Addepalli, G Ormazabal, ...
IEEE Design & Test 30 (2), 35-44, 2013
372013
Architecture support for dynamic integrity checking
AK Kanuparthi, M Zahran, R Karri
IEEE Transactions on information forensics and security 7 (1), 321-332, 2011
262011
A high-performance, low-overhead microarchitecture for secure program execution
AK Kanuparthi, R Karri, G Ormazabal, SK Addepalli
2012 IEEE 30th International Conference on Computer Design (ICCD), 102-107, 2012
192012
Feasibility study of dynamic trusted platform module
AK Kanuparthi, M Zahran, R Karri
2010 IEEE International Conference on Computer Design, 350-355, 2010
192010
Techniques for Preventing Memory Timing Attacks
A Kanuparthi, N Kodalapura
US Patent 10,116,436, 2018
15*2018
Did we learn from LLC Side Channel Attacks? A Cache Leakage Detection Tool for Crypto Libraries
G Irazoqui, K Cong, X Guo, H Khattri, A Kanuparthi, T Eisenbarth, B Sunar
ArXiv, 2017
122017
Controlling Your Control Flow Graph
A Kanuparthi, J Rajendran, R Karri
Hardware Oriented Security and Trust, 6, 2016
82016
A survey of microarchitecture support for embedded processor security
AK Kanuparthi, R Karri, G Ormazabal, SK Addepalli
2012 IEEE Computer Society Annual Symposium on VLSI, 368-373, 2012
72012
Hardware based technique to prevent critical fine-grained cache side-channel attacks
A Basak, A Kanuparthi, NN Kodalapura, JM Fung
US Patent 11,144,468, 2021
62021
Formal verification of security critical hardware-firmware interactions in commercial SoCs
S Ray, N Ghosh, RJ Masti, A Kanuparthi, JM Fung
2019 56th ACM/IEEE Design Automation Conference (DAC), 1-4, 2019
62019
Did we learn from LLC side channel attacks
G Irazoqui, K Cong, X Guo, H Khattri, AK Kanuparthi, T Eisenbarth, ...
A Cache Leakage Detection Tool for Crypto Libraries. arXiv abs/1709.01552, 2017
62017
Rtl-contest: Concolic testing on rtl for detecting security vulnerabilities
X Meng, S Kundu, AK Kanuparthi, K Basu
IEEE Transactions on Computer-Aided Design of Integrated Circuits and …, 2021
52021
When a patch is not enough-hardfails: Software-exploitable hardware bugs
G Dessouky, D Gens, P Haney, G Persyn, A Kanuparthi, H Khattri, ...
arXiv preprint arXiv:1812.00197, 2018
42018
Reliable Integrity Checking in Multicore Processors
A Kanuparthi, R Karri
ACM Transactions on Architecture and Code Optimization (TACO), 23, 2015
42015
Carry-Out Interference Optimization in WCRT Analysis for Global Fixed-Priority Multiprocessor Scheduling..................
H An, MS Al-Mamun, MK Orlowski, L Liu, Y Yi, K Chang, S Sinha, B Cline, ...
1
Techniques for preventing memory timing attacks
NN Kodalapura, A Kanuparthi
US Patent App. 17/384,268, 2021
2021
Techniques for preventing memory timing attacks
NN Kodalapura, A Kanuparthi
US Patent 11,121,853, 2021
2021
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Articles 1–20