| Understanding graphs in EDA: From shallow to deep learning Y Ma, Z He, W Li, L Zhang, B Yu Proceedings of the 2020 international symposium on physical design, 119-126, 2020 | 43 | 2020 |
| FPGA-based real-time super-resolution system for ultra high definition videos Z He, H Huang, M Jiang, Y Bai, G Luo 2018 IEEE 26th Annual International Symposium on Field-Programmable Custom …, 2018 | 25 | 2018 |
| Learn to floorplan through acquisition of effective local search heuristics Z He, Y Ma, L Zhang, P Liao, N Wong, B Yu, MDF Wong 2020 IEEE 38th International Conference on Computer Design (ICCD), 324-331, 2020 | 24 | 2020 |
| Chateda: A large language model powered autonomous agent for eda H Wu, Z He, X Zhang, X Yao, S Zheng, H Zheng, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2024 | 21 | 2024 |
| Functionality matters in netlist representation learning Z Wang, C Bai, Z He, G Zhang, Q Xu, TY Ho, B Yu, Y Huang Proceedings of the 59th ACM/IEEE Design Automation Conference, 61-66, 2022 | 21 | 2022 |
| Graph learning-based arithmetic block identification Z He, Z Wang, C Bai, H Yang, B Yu 2021 IEEE/ACM International Conference On Computer Aided Design (ICCAD), 1-8, 2021 | 18 | 2021 |
| Reinforcement learning driven physical synthesis Z He, L Zhang, P Liao, Y Ma, B Yu 2020 IEEE 15th International Conference on Solid-State & Integrated Circuit …, 2020 | 10 | 2020 |
| Physical synthesis for advanced neural network processors Z He, P Liao, S Liu, Y Ma, Y Lin, B Yu Proceedings of the 26th Asia and South Pacific Design Automation Conference …, 2021 | 9 | 2021 |
| X-Check: GPU-Accelerated Design Rule Checking via Parallel Sweepline Algorithms Z He, Y Ma, B Yu Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided …, 2022 | 5 | 2022 |
| AlphaSyn: Logic synthesis optimization with efficient monte carlo tree search Z Pei, F Liu, Z He, G Chen, H Zheng, K Zhu, B Yu 2023 IEEE/ACM International Conference on Computer Aided Design (ICCAD), 1-9, 2023 | 3 | 2023 |
| Efficient super-resolution system with block-wise hybridization and quantized winograd on fpga B Shi, J Zhang, Z He, X Wei, S Li, G Luo, H Zheng, Y Xie IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2023 | 3 | 2023 |
| Deep model compression and inference speedup of sum–product networks on tensor trains CY Ko, C Chen, Z He, Y Zhang, K Batselier, N Wong IEEE transactions on neural networks and learning systems 31 (7), 2665-2671, 2019 | 3 | 2019 |
| OpenDRC: An Efficient Open-Source Design Rule Checking Engine with Hierarchical GPU Acceleration Z He, Y Zuo, J Jiang, H Zheng, Y Ma, B Yu 2023 60th ACM/IEEE Design Automation Conference (DAC), 1-6, 2023 | 2 | 2023 |
| AutoGraph: optimizing DNN computation graph for parallel GPU kernel execution Y Zhao, Q Sun, Z He, Y Bai, B Yu Proceedings of the AAAI Conference on Artificial Intelligence 37 (9), 11354 …, 2023 | 2 | 2023 |
| Efficient arithmetic block identification with graph learning and network-flow Z Wang, Z He, C Bai, H Yang, B Yu IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, 2022 | 2 | 2022 |
| Large Language Models for EDA: Future or Mirage? Z He, B Yu | 1 | 2024 |
| Bit-Level Quantization for Efficient Layout Hotspot Detection Z Pei, W Zhao, Z He, B Yu 2023 International Symposium of Electronics Design Automation (ISEDA), 465-470, 2023 | 1 | 2023 |
| Fpga acceleration for computational glass-free displays Z He, G Luo Proceedings of the 2017 ACM/SIGDA International Symposium on Field …, 2017 | 1 | 2017 |
| CBTune: Contextual Bandit Tuning for Logic Synthesis F Liu, Z Pei, Z Yu, H Zheng, Z He, T Chen, B Yu | | 2024 |
| LSTP: A Logic Synthesis Timing Predictor H Zheng, Z He, F Liu, Z Pei, B Yu | | 2024 |
Bei YuThe Chinese University of Hong KongVerified email at cse.cuhk.edu.hk
