| High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler, MA Franklin, RD Chamberlain US Patent 7,921,046, 2011 | 304 | 2011 |
| Intelligent data storage and processing using fpga devices R Chamberlain, B Brink, J White, M Franklin, R Cytron US Patent App. 10/550,326, 2007 | 284 | 2007 |
| Method and system for high throughput blockwise independent encryption/decryption DE Taylor, RS Indeck, JR White, RD Chamberlain US Patent 8,379,841, 2013 | 240 | 2013 |
| Method and apparatus for performing similarity searching on a data stream with respect to a query string JD Buhler, RD Chamberlain, MA Franklin, K Gyang, AC Jacob, ... US Patent 7,917,299, 2011 | 240 | 2011 |
| Intelligent data storage and processing using FPGA devices RD Chamberlain, MA Franklin, RS Indeck, RK Cytron, SR Cholleti US Patent 8,095,508, 2012 | 228 | 2012 |
| Firmware socket module for FPGA-based pipeline processing RD Chamberlain, EFB Shands, BC Brodie, M Henrichs, JR White US Patent 7,954,114, 2011 | 214 | 2011 |
| High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler, MA Franklin, RD Chamberlain US Patent 8,478,680, 2013 | 194 | 2013 |
| High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler, MA Franklin, RD Chamberlain US Patent 8,595,104, 2013 | 174* | 2013 |
| Method and apparatus for processing financial information at hardware speeds using FPGA devices RS Indeck, RK Cytron, MA Franklin, RD Chamberlain US Patent 8,069,102, 2011 | 171 | 2011 |
| Associative database scanning and information retrieval using FPGA devices RS Indeck, RK Cytron, MA Franklin, RD Chamberlain US Patent 7,139,743, 2006 | 164 | 2006 |
| Parallel simulated annealing using speculative computation EE Witte, RD Chamberlain, MA Franklin IEEE Transactions on Parallel & Distributed Systems 2 (04), 483-494, 1991 | 153 | 1991 |
| High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler, MA Franklin, RD Chamberlain US Patent 8,600,856, 2013 | 150 | 2013 |
| Parallel logic simulation of VLSI systems ML Bailey, JV Briner Jr, RD Chamberlain ACM Computing Surveys (CSUR) 26 (3), 255-294, 1994 | 146 | 1994 |
| Auto-compensating capacitive level sensor RA Livingston, RD Chamberlain US Patent 6,539,797, 2003 | 143 | 2003 |
| Method and Apparatus for Protein Sequence Alignment using FPGA Devices R Chamberlain, J Buhler, A Jacob, J Lancaster, B Harris US Patent App. 11/836,947, 2008 | 139 | 2008 |
| Oil level control system GT Seener, JH Heffner, RD Chamberlain, DC Macke Sr, RA Livingston US Patent 6,125,642, 2000 | 134 | 2000 |
| Intelligent data storage and processing using FPGA devices RD Chamberlain, MA Franklin, RS Indeck, RK Cytron, SR Cholleti US Patent 8,751,452, 2014 | 129 | 2014 |
| High speed processing of financial information using FPGA devices S Parsons, DE Taylor, DV Schuehler, MA Franklin, RD Chamberlain US Patent 8,458,081, 2013 | 124 | 2013 |
| Biosequence Similarity Search on the Mercury System P Krishnamurthy, J Buhler, R Chamberlain, M Franklin, K Gyang, A Jacob, ... The Journal of VLSI Signal Processing Systems for Signal, Image, and Video …, 2007 | 115 | 2007 |
| Mercury BLASTP: Accelerating protein sequence alignment A Jacob, J Lancaster, J Buhler, B Harris, RD Chamberlain ACM Transactions on Reconfigurable Technology and Systems (TRETS) 1 (2), 1-44, 2008 | 107 | 2008 |
Jeremy Buhlerprofessor of computer science, Washington universityVerified email at wustl.edu
