| A 56.4-to-63.4 GHz multi-rate all-digital fractional-N PLL for FMCW radar applications in 65 nm CMOS W Wu, RB Staszewski, JR Long IEEE Journal of solid-state circuits 49 (5), 1081-1096, 2014 | 202 | 2014 |
| A 28-nm 75-fsrms Analog Fractional- Sampling PLL With a Highly Linear DTC Incorporating Background DTC Gain Calibration and Reference Clock Duty Cycle … W Wu, CW Yao, K Godbole, R Ni, PY Chiang, Y Han, Y Zuo, A Verma, ... IEEE Journal of Solid-State Circuits 54 (5), 1254-1265, 2019 | 151 | 2019 |
| 9.6 A 2.7-to-4.3 GHz, 0.16 psrms-jitter,− 246.8 dB-FOM, digital fractional-N sampling PLL in 28nm CMOS X Gao, O Burg, H Wang, W Wu, CT Tu, K Manetakis, F Zhang, L Tee, ... 2016 IEEE International Solid-State Circuits Conference (ISSCC), 174-175, 2016 | 96 | 2016 |
| High-Resolution Millimeter-Wave Digitally Controlled Oscillators With Reconfigurable Passive Resonators W Wu, JR Long, RB Staszewski IEEE Journal of Solid-State Circuits 48 (11), 2785-2794, 2013 | 88 | 2013 |
| A 14-nm 0.14-psrmsFractional-N Digital PLL With a 0.2-ps Resolution ADC-Assisted Coarse/Fine-Conversion Chopping TDC and TDC Nonlinearity Calibration CW Yao, R Ni, C Lau, W Wu, K Godbole, Y Zuo, S Ko, NS Kim, S Han, I Jo, ... IEEE Journal of Solid-State Circuits 52 (12), 3446-3457, 2017 | 72 | 2017 |
| A 14-nm Ultra-Low Jitter Fractional-N PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO W Wu, CW Yao, C Guo, PY Chiang, L Chen, PK Lau, Z Bai, SW Son, ... IEEE Journal of Solid-State Circuits 56 (12), 3756-3767, 2021 | 68 | 2021 |
| Passive circuit technologies for mm-wave wireless systems on silicon JR Long, Y Zhao, W Wu, M Spirito, L Vera, E Gordon IEEE Transactions on Circuits and Systems I: Regular Papers 59 (8), 1680-1693, 2012 | 64 | 2012 |
| A 56.4-to-63.4 GHz spurious-free all-digital fractional-N PLL in 65nm CMOS W Wu, X Bai, RB Staszewski, JR Long 2013 IEEE International Solid-State Circuits Conference Digest of Technical …, 2013 | 57 | 2013 |
| A 16-channel, 28/39GHz dual-polarized 5G FR2 phased-array transceiver IC with a quad-stream IF transceiver supporting non-contiguous carrier aggregation up to 1.6 GHz BW A Verma, V Bhagavatula, A Singh, W Wu, H Nagarajan, PK Lau, X Yu, ... 2022 IEEE International Solid-State Circuits Conference (ISSCC) 65, 1-3, 2022 | 44 | 2022 |
| 32.2 A 14nm analog sampling fractional-N PLL with a digital-to-time converter range-reduction technique achieving 80fs integrated jitter and 93fs at near-integer channels W Wu, CW Yao, C Guo, PY Chiang, PK Lau, L Chen, SW Son, TB Cho 2021 IEEE International Solid-State Circuits Conference (ISSCC) 64, 444-446, 2021 | 43 | 2021 |
| 9.4 A 28nm CMOS digital fractional-N PLL with− 245.5 dB FOM and a frequency tripler for 802.11 abgn/ac radio X Gao, L Tee, W Wu, KS Lee, AA Paramanandam, A Jha, N Liu, E Chan, ... 2015 IEEE International Solid-State Circuits Conference-(ISSCC) Digest of …, 2015 | 38 | 2015 |
| 17GHz RF Front-Ends for Low-Power Wireless Sensor Networks W Wu, M Sanduleanu, X Li Proc. 2007 IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 164-167, 0 | 27* | |
| A mm-wave FMCW radar transmitter based on a multirate ADPLL W Wu, X Bai, RB Staszewski, JR Long 2013 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 107-110, 2013 | 26 | 2013 |
| Energy-efficient wireless front-end concepts for ultra lower power radio JR Long, W Wu, Y Dong, Y Zhao, MAT Sanduleanu, JFM Gerrits, ... 2008 IEEE Custom Integrated Circuits Conference, 587-590, 2008 | 25 | 2008 |
| System and method for fast converging reference clock duty cycle correction for digital to time converter (DTC)-based analog fractional-N phase-locked loop (PLL) W Wu, CW Yao US Patent 10,581,418, 2020 | 22 | 2020 |
| High-resolution 60-GHz DCOs with reconfigurable distributed metal capacitors in passive resonators W Wu, JR Long, RB Staszewski, JJ Pekarik 2012 IEEE Radio Frequency Integrated Circuits Symposium, 91-94, 2012 | 21 | 2012 |
| High resolution millimeter wave digitally controlled oscillator with reconfigurable distributed metal capacitor passive resonators W Wu, JR Long, RB Staszewski US Patent 9,118,335, 2015 | 18 | 2015 |
| A digital ultra-fast acquisition linear frequency modulated PLL for mm-wave FMCW radars W Wu, JR Long, RB Staszewski 2009 IEEE International Symposium on Radio-Frequency Integration Technology …, 2009 | 17 | 2009 |
| Low-jitter frequency generation techniques for 5G communication: A tutorial W Wu IEEE Solid-State Circuits Magazine 13 (4), 44-63, 2021 | 14 | 2021 |
| A 5.5-7.3 GHz Analog Fractional-N Sampling PLL in 28-nm CMOS with 75 fsrmsJitter and −249.7 dB FoM W Wu, CW Yao, K Godbole, R Ni, PY Chiang, Y Han, Y Zuo, A Verma, ... 2018 IEEE Radio Frequency Integrated Circuits Symposium (RFIC), 6403-6408, 2018 | 14 | 2018 |
Robert Bogdan StaszewskiUniversity College Dublin (UCD)Verified email at ucd.ie
