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Mohamed Eldafrawy
Mohamed Eldafrawy
Deep Learning Compiler Engineer, Groq Inc
Verified email at mail.utoronto.ca
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VTR 8: High-performance CAD and Customizable FPGA Architecture Modelling
KE Murray, O Petelin, S Zhong, JM Wang, M Eldafrawy, JP Legault, E Sha, ...
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (2), 1-55, 2020
2252020
FPGA Logic Block Architectures for Efficient Deep Learning Inference
M Eldafrawy, A Boutros, S Yazdanshenas, V Betz
ACM Transactions on Reconfigurable Technology and Systems (TRETS) 13 (3), 1-34, 2020
302020
Math Doesn't Have to be Hard: Logic Block Architectures to Enhance Low-Precision Multiply-Accumulate on FPGAs
A Boutros, M Eldafrawy, S Yazdanshenas, V Betz
Proceedings of the 2019 ACM/SIGDA International Symposium on Field …, 2019
262019
3D Convolutional Neural Network (CNN) Implementation on Systolic Array-Based FPGA Overlay CNN Accelerator
JH Kim, MBM Eldafrawy, T Ariyanayagam, AR Rooney
US Patent App. 18/129,341, 2023
12023
An event-based Network-on-Chip debugging system for FPGA-based MPSoCs
J Rettkowski, M Eldafrawy, D Göhringer
2017 International Conference on Embedded Computer Systems: Architectures …, 2017
12017
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